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74AC251 * 74ACT251 8-Input Multiplexer with 3-STATE Output
November 1988 Revised November 1999
74AC251 * 74ACT251 8-Input Multiplexer with 3-STATE Output
General Description
The AC/ACT251 is a high-speed 8-input digital multiplexer. It provides, in one package, the ability to select one bit of data from up to eight sources. It can be used as universal function generator to generate any logic function of four variables. Both true and complementary outputs are provided.
Features
s ICC reduced by 50% s Multifunctional capability s On-chip select logic decoding s Inverting and noninverting 3-STATE outputs s Outputs source/sink 24 mA s ACT251 has TTL-compatible inputs
Ordering Code:
Order Number 74AC251SC 74AC251SJ 74AC251MTC 74AC251PC 74ACT251SC 74ACT251MTC 74ACT251PC Package Number M16A M16D MTC16 N16E M16A MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names S0-S2 OE I0-I7 Z Z Select Inputs 3-STATE Output Enable Input Multiplexer Inputs 3-STATE Multiplexer Output Complementary 3-STATE Multiplexer Output Description
FACT is a trademark of Fairchild Semiconductor Corporation.
(c) 1999 Fairchild Semiconductor Corporation
DS009945
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74AC251 * 74ACT251
Functional Description
This device is a logical implementation of a single-pole, 8position switch with the switch position controlled by the state of three Select inputs, S0, S1, S2. Both true and complementary outputs are provided. The Output Enable input (OE) is active LOW. When it is activated, the logic function provided at the output is: Z = OE * (I0 * S0 * S1 * S2 + I1* S0 * S1 * S2 + I2 * S0 * S1 * S2 + I3 * S0 * S1 * S2 + I4 * S0 * S1 * S2 + I5 * S0 * S1 * S2 + I6 * S0 * S1 * S2 + I7 * S0 * S1 * S2) When the Output Enable is HIGH, both outputs are in the high impedance (High Z) state. This feature allows multiplexer expansion by tying the outputs of up to 128 devices together. When the outputs of the 3-STATE devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. The Output Enable signals should be designed to ensure there is no overlap in the active-LOW portion of the enable voltages.
Truth Table
Inputs OE H L L L L L L L L S2 X L L L L H H H H S1 X L L H H L L H H S0 X L H L H L H L H Z Z I0 I1 I2 I3 I4 I5 I6 I7 Outputs Z Z I0 I1 I2 I3 I4 I5 I6 I7
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74AC251 * 74ACT251
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) PDIP 140C 50 mA -65C to +150C 50 mA -20 mA +20 mA -0.5V to VCC + 0.5V -20 mA +20 mA -0.5V to VCC + 0.5V -0.5V to +7.0V
Recommended Operating Conditions
Supply Voltage (VCC) AC ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (V/t) ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC -40C to +85C
125 mV/ns
DC Electrical Characteristics for AC
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN (Note 4) IOZ Maximum Input Leakage Current Maximum 3-STATE Current IOLD IOHD Minimum Dynamic Output Current (Note 3) 5.5 5.5 5.5 5.5 4.0 0.25 2.5 75 -75 40.0 A mA mA A 5.5 0.002 0.001 0.001 TA = +25C Typ 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 0.1 TA = -40C to +85C Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 VIN = VIL or VIH 2.46 3.76 4.76 0.1 0.1 0.1 VIN = VIL or VIH 0.44 0.44 0.44 1.0 A V IOL = 12 mA IOL = 24 mA IOL = 24 mA (Note 2) VI = VCC, GND VI (OE) = VIL, VIH VI = VCC, VGND VO = VCC, GND VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND V IOUT = 50 A V IOH = -12 mA IOH = -24 mA IOH = -24 mA (Note 2) V IOUT = -50 A V VOUT = 0.1V or VCC - 0.1V V Units Conditions VOUT = 0.1V or VCC - 0.1V
ICC (Note 4) Maximum Quiescent Supply Curent
Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
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74AC251 * 74ACT251
DC Electrical Characteristics for ACT
Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN IOZ ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum 3-STATE Current Maximum ICC/Input Minimum Dynamic Output Current (Note 6) Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 5.5 5.5 4.0 0.6 0.001 0.001 TA = +25C Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 0.1 0.5 TA = -40C to +85C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 1.0 5.0 1.5 75 -75 40.0 A A mA mA mA A V Units V V V Conditions VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50 A VIN = VIL or VIH V IOH = -24 mA IOH = -24 mA (Note 5) IOUT = 50 A VIN = VIL or VIH V IOL = 24 mA IOL = 24 mA (Note 5) VI = VCC, GND VI = VIL, VIH VO = VCC, GND VI = VCC - 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND
Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
VCC Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay Sn to Z or Z Propagation Delay Sn to Z or Z Propagation Delay In to Z or Z Propagation Delay In to Z or Z Output Enable Time OE to Z or Z Output Enable Time OE to Z or Z Output Disable Time OE to Z or Z Output Disable Time OE to Z or Z
Note 7: Voltage Range 3.3 is 3.3V 0.3V. Voltage Range 5.0 is 5.0V 0.5V
TA = +25C CL = 50 pF Min 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 Typ 11.5 8.5 11.0 8.0 10.0 7.0 9.0 6.5 7.5 5.5 7.5 5.5 8.5 7.0 7.0 5.5 Max 17.5 12.5 17.5 12.5 14.0 10.0 14.0 10.0 11.0 8.0 11.0 8.0 11.5 9.5 11.0 8.0
TA = -40C to +85C CL = 50 pF Min 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 Max 19.0 13.5 19.0 13.5 15.5 11.0 15.5 11.0 12.0 9.0 12.0 9.0 13.0 10.0 12.0 8.5 ns ns ns ns ns ns ns ns Units
(V) (Note 7) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
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74AC251 * 74ACT251
AC Electrical Characteristics for ACT
V CC Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay Sn to Z or Z Propagation Delay Sn to Z or Z Propagation Delay In to Z or Z Propagation Delay In to Z or Z Output Enable Time OE to Z or Z Output Enable Time OE to Z or Z Output Disable Time OE to Z or Z Output Disable Time OE to Z or Z
Note 8: Voltage Range 5.0 is 5.0V 0.5V
TA = +25C CL = 50 pF Min 2.5 2.5 2.5 2.5 1.5 1.5 2.0 1.5 Typ 7.0 7.5 5.5 6.5 5.0 4.5 6.0 4.5 Max 15.5 16.5 12.0 12.5 8.5 8.5 12.0 8.5
TA = -40C to +85C CL = 50 pF Min 2.0 2.5 2.0 2.5 1.5 1.5 2.0 1.5 Max 17.0 18.5 13.0 14.0 9.0 9.5 13.0 9.0 ns ns ns ns ns ns ns ns Units
(V) (Note 8) 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0
Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 70.0 Units pF pF V CC = OPEN V CC = 5.0V Conditions
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74AC251 * 74ACT251
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body Package Number M16A
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74AC251 * 74ACT251
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ Type II, 5.3mm Wide Package Number M16D
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74AC251 * 74ACT251
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Packge (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16
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74AC251 * 74ACT251 8-Input Multiplexer with 3-STATE Output
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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